The present invention is related to integrated circuit memories, and, more particularly, to a circuit for aligning both the rising and falling edges of data signals in DDR (Double Data Rate) integrated circuit memories.
As the frequency of DDR memories continues to increase, the precise alignment of both the rising edge and falling edge of the output data to the rising and falling edges of the system clock has become very critical since data must be captured by both edges of the clock. Delay Locked Loops (DLLs) have been used to adjust the timing of the output data such that it aligns with the system clock. Until recently, only the rising edge of the data has been aligned with the rising edge of the system clock by the DLL. Circuit techniques have been used to maintain the duty cycle of the output data at 50% so that the falling edge of the data will align with the falling edge of the 50% duty cycle system clock. FIG. 1 shows a typical Voltage Controlled DLL used in recent DDR memory devices.
The Voltage Controlled DLL 100 of FIG. 1 includes an input clock buffer 102, a phase detector 104, a variable delay line 106, a control voltage generator 108, a replica fixed delay line 110, and an output data path block 112.
Referring to FIG. 1, it can be seen that when the DLL is locked, the signals DLLCLK and SYNC at the input of phase detector 104 are in phase, which means that:tvar=ntck−tfix, where tck is the clock period.The delay between the external clock ExCLK and the data output is:tbuf+tvar+tout=tbuf+(ntck−tfix)+tout.If tfix=tbuf+tout, the delay between ExCLK and the data output is ntck, and the output data will be precisely aligned with the external clock. It is very difficult to have tfix precisely match tbuf+tout under all conditions unless an exact replica of the clock buffer and data output path are used to implement the fixed delay. In addition, since only the rising edge of SYNC is aligned with DLLCLK, any duty cycle distortion introduced by the clock buffer, variable delay, and output path will result in the falling edge data undesirably not being aligned with the falling edge of the system clock.
For double data rate outputs, data is output on the rising and falling edge of the system clock. In the discussion below, the term “rising edge” data refers to data that is output on the rising edge of the system clock. The term “falling edge” data refers to data that is output on the falling edge of the system clock.
FIG. 2 is a prior art DLL (U.S. Pat. No. 7,028,208 B2) that addresses most of the limitations of the DLL of FIG. 1. DLL 200 includes input buffers 202 and 204, a coarse delay line/phase detect block 206, a converter 208, fine delay line/phase detect blocks 210 and 212, converters 214 and 216, a clock driver 218, I/O model 220, a clock driver 218, data latch 222, and a data driver 224.
The circuit 200 of FIG. 2 has the goal of precisely aligning the rising and falling edge of the output data with the system clock signal, even if the clock signal is not precisely 50% duty cycle. If the clock is precisely 50% duty cycle, the intention is to have the output also be 50%.
However, circuit 200 of FIG. 2 has two major limitations.
Firstly, the two RX Buffers 202 and 204 must produce the reference clocks CLKIN− and CLKIN+ without introducing any duty cycle distortion relative to the input clocks since these are the references to which the outputs are effectively aligned by the fine DL/PD circuits. Since two separate buffers 202 and 204 are required to generate these references and they are responding to complementary input clock signals, it is inevitable that duty cycle distortion will be introduced in these reference signals with respect to each other. This distortion will show up in the output signal. If a single ended input clock signal were used and its rising and falling edges were the source of the reference signals, the input would still have to be buffered and distortion would again be introduced.
Secondly, the output of the “I/O Model” 220, which is the feedback signal, is converted into a rising edge signal (CLKFB+) and a falling edge signal (CLKFB−). If CLKIN+ and CLKIN− are perfect representations of the duty cycle of the input clocks, but the time between the rising edges of CLKFB+ and CLKFB− does not precisely track the high time of the output of the I/O Model 220, duty cycle distortion in the feedback signal not present in the output path will be introduced. The DLL 200 will remove the distortion in the feedback signal, but this effectively introduces distortion into the data out signal. It is inevitable that the circuit block, “CONVERTER” 216, will introduce duty cycle distortion.
What is desired, therefore, is a DLL circuit capable of effectively aligning both the rising edge and falling edge of data signals in a DDR memory, and without introducing undesirable duty cycle distortion.